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Altera_Forum's avatar
Altera_Forum
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18 years ago

No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Well, i've tried to change any and all settings but i can't delay the clock signal or the data signals! I've tried Tco and min Tco as well as the maximum/minimum output delay. Any timing assignments entered in the assignment editor are flagged as invalid ("No timing path applicable to specified source and destination") and none of the output delay options actually has any effect on the output signals!

Any idea what could be wrong here? All i need to do is to delay the output clock by 5ns to fix the current hold problem...