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Hold time defines a relationship between the clock and data arriving at a register.
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Does it? Doesn't it define the time between the clock edge and the point in time the data is *removed* from the destination register's input? I.e. the time the data must be stable after the clock such that the receiving register will have enough time to latch the data. The setup time would be the time between the data is valid and the clock edge that acts on the data. This what confuses me.
Since i want to (first) make sure that my internal signals have a 5 ns hold time i should be able to specify in the assignment editor that Th between the clock and a certain data signal should be 4ns. Or perhaps Quartus tries to be smart and *removes* the hold time on internal nodes because it knows it is not required by the internal FFs?
I also do not understand what the point is to specify a certain Th on INPUT ports since Th on an input port is defined by the external driver - no setting in Quartus will change the external device behavior. The only way i can see Th specified on an input port is if Quartus II will actually internally generate a FF to buffer the data but if this is done the data should be delayed by an additional clock cycle which is clearly not what we want.
Any clarification or pointers to decent documentation on this subject is greatly appreciated.
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