No timing path applicable to specified source and destination

I'm not sure what you mean about why can't you specify an external hold time? Hold time defines a relationship between the clock and data arriving at a register. Since you're sending data off chip, the hold time would technically be applied to the downstream register, off chip. This is what external assignments do, basically describe an external register and what it's timing is. But if you want to describe things in terms of the FPGA, Tco and Min Tco are what you want. Bottom line is hold isn't meant to work on output pins, but the other two types of assignments are and should be used. Good luck.