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The said constraint could be achieved with Output_Minimum_Delay (data) respectivly Output_Maxmum_Delay (clock) assignments, hold_time anysis is related to internal registers only.
Before defining any constraints in detail, you should consider which timing could be expected normally respectively how to conncted the logic to achieve an intended timing relation. E. g. if clock output is connected to a global clock and data sourced from registers clocked with the same clock, you could expect the intended timing as normal behaviour.
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I don't understand why i can't specify a certain hold time on the output registers in the FPGA. In this case, i'm using the LAI to look at the output signals so i want the correct setup and hold times to be existent not only at the actual external output signals but also on the corresponding LAI signals.
I tried to assign setup and hold times to the data path earlier inside the FPGA but the result is the same; the assignments are ignored by Quartus II.
I will look at the output max/min delay settings too.
Thanks.
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