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Altera_Forum's avatar
Altera_Forum
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18 years ago

No timing path applicable to specified source and destination

I'm trying to achieve a 4ns hold timing on an external output-only data bus and an output-only clock that are both driven from my Cyclone II FPGA. I'm assigning the following th settings in Quartus I...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

If you're doing device-centric constraints(like Tsu and Th on the input ports), then on the output side you want to use Tco and Min Tco constraints. Most user's just apply Tco and Min Tco directly to the port(in the To column, as all single-point assignments are there), and leave it at that. (And as always look at TimeQuest when you get a chance...)