No timing path applicable to specified source and destination

The said constraint could be achieved with Output_Minimum_Delay (data) respectivly Output_Maxmum_Delay (clock) assignments, hold_time anysis is related to internal registers only.

Before defining any constraints in detail, you should consider which timing could be expected normally respectively how to conncted the logic to achieve an intended timing relation. E. g. if clock output is connected to a global clock and data sourced from registers clocked with the same clock, you could expect the intended timing as normal behaviour.