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Altera_Forum's avatar
Altera_Forum
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11 years ago

No output in simulation for Division implemented using IP Core

hello everyone, I have design the division module with the help of lpm_divide. I am using Quartus Prime Lite Edition. I have done simulation on ModelSim Altera Starter Edition. i am getting only High Impedence at the output. What can be the problem?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Could you provide more detailed information: have you forced any values, cause modeling start with 'U' value in simualtion, you don't have 'z' i assume.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    Could you provide more detailed information: have you forced any values, cause modeling start with 'U' value in simualtion, you don't have 'z' i assume.

    --- Quote End ---

    If it is Verilog, then the value may be 'Z' as there is no 'U'