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Altera_Forum
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13 years ago

No Output from my VHDL code !?

Hello all, Being a newbie in VHDL, I am sure theres a stupid mistake somewhere. I just can not get my head around it. There is no output . I am using activehdl as the compiling tool and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

And you also need to learn the difference between signals and variables.

Signals are only updated at the end of the process, so y will just take the value of (x(N-1) or y) because it wont be updated until the process suspends