Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

No Output from my VHDL code !?

Hello all, Being a newbie in VHDL, I am sure theres a stupid mistake somewhere. I just can not get my head around it. There is no output . I am using activehdl as the compiling tool and ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Its probably because you forgot to put y in the sensitivity list. But why are you anding y with iteself?

And the second bit of code is invalid because it is not inside a process.