Honored Contributor
Honored ContributorThanks for taking the time to review the file.
The du_forum.vhd file you reviewed is the top level entity. I checked the pinout assignments and confirmed that VID_OUT, VCLK, HSYNC, and VSYNC are assigned to pins on the FPGA. All of these should be changed by the process. It looks like nothing in the process after ELSIF (CLKOUT'EVENT AND CLKOUT='1') is being recognized because these warning messages are generated: Warning: Output pins are stuck at VCC or GND Warning (13410): Pin "VCLK" is stuck at GND Warning (13410): Pin "HSYNC" is stuck at GND Warning (13410): Pin "VSYNC" is stuck at GND Warning (13410): Pin "VID_OUT[0]" is stuck at GND Warning (13410): Pin "VID_OUT[1]" is stuck at GND Warning (13410): Pin "VID_OUT[2]" is stuck at GND Warning (13410): Pin "VID_OUT[3]" is stuck at GND Also, there are warnings that all the RAM nodes, q[], are synthesized away, which is consistent because if the CLKOUT part of the process isn't executed, nothing ever reads the RAM.
