"No output dependent on input pin" error

I don't know vhdl (only verilog). But here is a stab at it.

1. It looks like your display process is the only part dependent on CLK_OUT.

2. Its functionality is to ultiimately set a new value in sVID_DWORD.

3. VID_OUT is assigned to sVID_DWORD.

4. VID_OUT is in your entity port list as an output.

Therefore, if you have not assigned VID_OUT to output pins in the higher level module which instantiates this one, the code will be optimized away.

Therefore, this would make sense:

Warning: Design contains 1 input pin(s) that do not drive logic

and so would:

Warning (15610): No output dependent on input pin "CLKOUT"

I'd check that you have correctly assigned the VID_OUT signal to actual hardware pins on the FPGA.