Honored ContributorHi. I have a GUI to let the user to enter the total no. bits of input. In verilog , normally we will declare no. of bits in top module by using parameter. So it it possible that the no of bits is the no. of bits entered by the user without declare the no.of bits first ? Thanks
Honored ContributorI don't think you can do that in hardware design. The interface of any module has to be constant. If you are an IP designer then you will go for that in software to let the user choose a given interface. But at the end the compiler wants to see a fixed interface.
You can use an alternative. Let your module have fixed maximum bits then pass a variable value to this bus.Honored ContributorIf the user entered "number of bits" results in new HDL being written out, resynthesized, fit, and a new engine, then you can allow a variable value(I have seen this implemented). In general you want to enter a value that encompasses all possible values the user could enter. Note that you're writing hardware, so there is no true "variability" like software. (Not that there aren't things to account for variablity, but it's hard).
Also be aware that if you don't define a width, the default is large. For example, I saw someone using tons of integers where they didn't define a range. Synthesis would build huge structures, then realize most of this wasn't necessary and synthesize it out. The synthesis took many times longer than the actual place and route, and took up Gigs of memory. By putting limits, things were much more managable.
