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JohanL's avatar
JohanL
Icon for New Contributor rankNew Contributor
4 years ago

No file related to error when running functional simulation.

I cannot get a proper waveform simulation for a project. I am running Quartus Lite 20.1. I have a larger project, but I opened a more basic sub-project in order to rule out some issues. I cr...
JohanL's avatar
JohanL
Icon for New Contributor rankNew Contributor
4 years ago

This may be a dumb question, but do all the blocks in a diagram need to be the same language type? i.e. all verilog or all vhdl? or does it not matter if they mix.

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

I believe they need to be the same. You must have only one language in a file.

You can have files of different languages though. As in, you can have 2 verilog design files and 3 vhdl design files in a project and it will be fine.

Can you attach your .qar file so I can see what's the problem? To generate a .qar file, go to Project>Archive Project.

Thanks,

Nurina

  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi,

    We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

    Regards,
    Nurina

    P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!