Forum Discussion

JohanL's avatar
JohanL
Icon for New Contributor rankNew Contributor
4 years ago

No file related to error when running functional simulation.

I cannot get a proper waveform simulation for a project. I am running Quartus Lite 20.1. I have a larger project, but I opened a more basic sub-project in order to rule out some issues. I cr...
JohanL's avatar
JohanL
Icon for New Contributor rankNew Contributor
4 years ago

This may be a dumb question, but do all the blocks in a diagram need to be the same language type? i.e. all verilog or all vhdl? or does it not matter if they mix.

Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
4 years ago

I believe they need to be the same. You must have only one language in a file.

You can have files of different languages though. As in, you can have 2 verilog design files and 3 vhdl design files in a project and it will be fine.

Can you attach your .qar file so I can see what's the problem? To generate a .qar file, go to Project>Archive Project.

Thanks,

Nurina