New Contributor
Regular ContributorHi,
RTL simulator is a simulator that captures the expected Register-Transfer Level behaviour of an FPGA design, which is what the Quartus University Program VWF does. So yes, they are connected.
From your error I think the problem is you named your signal "out", and this is illegal in VHDL/Verilog as that is a reserved name. Try renaming it out1 or anything else, I think that should solve your problem. BTW "in" is also a reserved signal name.
I think you designed your project using .bdf right? The downside of this is that Quartus will compile it as .bdf design, and show you a clean compilation based on bdf rules. But the University Program will convert the design to VHDL/Verilog code first, and then make a testbench based on the code and run the simulation for you, here it will compile the files using VHDL/Verilog rules and you will see the errors here.
Regards,
Nurina
New ContributorHello,
I do not have any pins labelled as "out" or "in". Maybe something is happening with the IP files I do not know.
I need to get actual data from this as deadlines draw near. I will learn the RTL simulation tool and hope it works.
If all else fails I will manually test the outputs in stages through an oscilloscope or do a fresh install and start over.
Thank you for all of your help and maybe at some point I will figure it out. After this project haha
