New Contributor
Regular ContributorHi,
RTL simulator is a simulator that captures the expected Register-Transfer Level behaviour of an FPGA design, which is what the Quartus University Program VWF does. So yes, they are connected.
From your error I think the problem is you named your signal "out", and this is illegal in VHDL/Verilog as that is a reserved name. Try renaming it out1 or anything else, I think that should solve your problem. BTW "in" is also a reserved signal name.
I think you designed your project using .bdf right? The downside of this is that Quartus will compile it as .bdf design, and show you a clean compilation based on bdf rules. But the University Program will convert the design to VHDL/Verilog code first, and then make a testbench based on the code and run the simulation for you, here it will compile the files using VHDL/Verilog rules and you will see the errors here.
Regards,
Nurina
New ContributorHello,
I do not have any pins labelled as "out" or "in". Maybe something is happening with the IP files I do not know.
I need to get actual data from this as deadlines draw near. I will learn the RTL simulation tool and hope it works.
If all else fails I will manually test the outputs in stages through an oscilloscope or do a fresh install and start over.
Thank you for all of your help and maybe at some point I will figure it out. After this project haha
New ContributorThis may be a dumb question, but do all the blocks in a diagram need to be the same language type? i.e. all verilog or all vhdl? or does it not matter if they mix.
Regular ContributorI believe they need to be the same. You must have only one language in a file.
You can have files of different languages though. As in, you can have 2 verilog design files and 3 vhdl design files in a project and it will be fine.
Can you attach your .qar file so I can see what's the problem? To generate a .qar file, go to Project>Archive Project.
Thanks,
Nurina
Regular ContributorHi,
We did not receive any response to the previous question/reply/answer that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.
Regards,
Nurina
P/S: If you like my comment, feel free to give Kudos. If my comment solved your problem, feel free to accept my comment as solution!
