No feasible entries for subprogram “CONV_INTEGER”

The problem is that you didnt include the std_logic_signed or std_logic_unsigned library (you cannot add both)

But just as a comment on the same theme - you shouldnt be using these libraries (and therefore conv_integer function) as it is not standard VHDL. You have also included both std_logic_arith and numeric_std which have conflicts, and so std_logic_arith should be removed (again, a non-standard library).

Then, to convert to an integer:

vr := to_integer( unsigned(R) );

or

vr := to_integer( signed(R) );

if you need a signed version.

The problem with std_logic_(un)signed is that you are limited to signed OR unsigned arithmatic in an entity. Numeric std defines both unsigned and signed types and therefor allows you to do both.

PS> You should remove the conv_std_logic_vector function too. Replace with:

B <= std_logic_vector( to_unsigned(vb, B'length) );

Or to minimuse on the type conversions, just use an integer on your ports. You dont have to use std_logic_vector everywhere.