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Altera_Forum
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15 years ago

No EPCS Layout Data

Hi all, I'm a newcomer to FPGA design - I have only been working with Altera's tools for a month or two. Excuse any 'noobness'. I'm working on a custom board that is designed around the C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

I'm a little confused as to what was working for you. I can explain what I saw when I used the serial flash programmer from the command line.

I had a distribution that contained and .elf, .sof, .cdf and .jic files. I was using the serial flash programmer from the command line. The programmer would actually claim that it successfully updated the flash - however, after a reset the FPGA was unable to configure from the flash device. In other words, the serial flash programmer is not a good way to tell if the flash chip is OK.

Are you in a position to try a new chip on your board?

Regards,

Seth