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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

NO clock event, but signal changes anyway!

In a nutshell, something weird is going on in my simulation... Clearly my code states that upon a rising_edge of nDB_BUF_EN then various outputs are latched. However I have seen the clocking si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

put some debug asserts in your code: 


process(nDB_BUF_EN)
begin
  if rising_edge(nDB_BUF_EN) then
    report "a Rising edge on nDB_BUF_EN just occured"
      severity Failure; --or note or warning or error if you want simulation to continue
  end if;
end process;