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Altera_Forum's avatar
Altera_Forum
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11 years ago

NO clock event, but signal changes anyway!

In a nutshell, something weird is going on in my simulation... Clearly my code states that upon a rising_edge of nDB_BUF_EN then various outputs are latched. However I have seen the clocking si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I agree with aprado, but what happens if the above is used and the nDB_BUF_EN is high for more than one clock cycle?

I suggest using a rising edge detector. Unless you are sure nDB_BUF_EN is never longer than one clock cycle high.