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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

NO clock event, but signal changes anyway!

In a nutshell, something weird is going on in my simulation... Clearly my code states that upon a rising_edge of nDB_BUF_EN then various outputs are latched. However I have seen the clocking si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Looks like this is very prone to glitches. You should'nt use logic as a clock.

Make a rising edge(CLK) and inside the rising_edge(CLK) put your if nDB_BUF_EN = '1' to latch the data.

It will generate FFs with an ENABLE port connected to the nDB_BUF_EN signal.