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Altera_Forum's avatar
Altera_Forum
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11 years ago

NO clock event, but signal changes anyway!

In a nutshell, something weird is going on in my simulation... Clearly my code states that upon a rising_edge of nDB_BUF_EN then various outputs are latched. However I have seen the clocking si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Using logic as a clock is a bad idea because it can be prone to glitching and variation in timing due to temperature and routing differences. It is much better practice to use it as a clock enable rather than a clock.