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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

NO clock event, but signal changes anyway!

In a nutshell, something weird is going on in my simulation... Clearly my code states that upon a rising_edge of nDB_BUF_EN then various outputs are latched. However I have seen the clocking si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

What type of simulation is it? RTL or gate level? Either way, your code can only clock if nDB_BUF_EN changes, so there must be a change somewhere.

Have you got a testbench so we can try and recreate the problem?