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Altera_Forum's avatar
Altera_Forum
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11 years ago

NO clock event, but signal changes anyway!

In a nutshell, something weird is going on in my simulation... Clearly my code states that upon a rising_edge of nDB_BUF_EN then various outputs are latched. However I have seen the clocking si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I am very suspicious of anything not named "clk" being used as a clock. If it is logic from elsewhere being used as a clock you're in for trouble. How are you trying to detect this glitch? how do you know the glitch isnt at a higher frequency than your detector can detect?

Is nDB_BUF_EN really a clock? is it some logic? how is it generated?