Honored ContributorHi, I'm being a total noob here and a dunce but I'll ask anyway. :) How come the vhdl code attached does not simulate properly. The syntax is correct and it compiles but the signal does not output on simulation. Please help and keep the roasting to a minimum. Thanks.
Honored ContributorIt looks fine to me. Show us how you simulate it and what results you are getting.
Honored ContributorHonored ContributorI never simulate in Quartus. But you can use the RTL viewer to see what Quartus has understood of your code and how it synthesized it. There must be something wrong in how your component has been instantiated in the project, or on how Quartus is simulating it.
Honored ContributorI have simulated your code using Modelsim-Altera Starter and it simulates as it is coded. When the gate is high the output follows the input as expected. When the gate is low the output is low as you have coded.
You stated "Hi, yeah the problem is that when I simulate using Quartus, even when both the input and gate are high, the output shows 0 transitions. Regardless of how I alter the inputs it always shows no transition. The problem is that it does not simulate properly. Has it simulated properly in your case? " It is to be expected that even when both the input and gate are high it will show no transitions on the output because the input is not transitioning. The ouput should follow the input as you have coded.
