New Contributor
Super ContributorThat's great but you still haven't explained how you are providing the 50MHz clock to the design in hardware or the code that you are using to help understand why this might be a software issue instead of a hardware issue. Just saying in Platform Designer "I'm using a 50 MHz clock" doesn't make it happen unless you are actually providing that in hardware.
New ContributorI am only working with GPIO pins; I have not attached any extra hardware to the FPGA (Cyclone V). Sorry, I am not getting your point. How do I provide a clock source on the hardware (FPGA)? I have also attached a part of the code to check if it’s a coding problem.
Super ContributorOK, on your board (is it a custom board or a development kit?), you have a clock signal going into clock pin(s) on the FPGA coming from, typically, a clock oscillator or crystal. What is that clock source and can you verify that it is providing the 50 MHz clock to the FPGA device that you expect?
Just because you are working on some GPIO signals doesn't mean you can ignore the overall design of the FPGA, including how it is clocked.
