newbie question: synchronous versus combinational bus mux using case statement

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This is a quirk of Verilog. Reg is just a data type in the Verilog. What it maps to in logic is down to the behavior in the code. It is just unfortunate they chose the name "reg"

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Yes, indeed, sir. I found both the code snippets below generate the desired combinational logic. I would guess the 2nd one might be frowned upon.

Would you be able to recommend a book that covers these sorts of issues? It would be nice to find one that is written in Verilog 2001.

Thanks again,

-J

    always @ (KEY,count)
    case(KEY)
    0    :    LED = count;
    1    :    LED = count;
    endcase

    always @ (KEY)
    case(KEY)
    0    :    LED = count;
    1    :    LED = count;
    endcase