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Altera_Forum
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8 years ago

newbie question: synchronous versus combinational bus mux using case statement

Hello all- Can anyone explain why the first (synchronous) version below compiles in quartus, but the second (combinational) does not? In the 2nd case the error is: Error (10137): Verilog ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

This is a quirk of Verilog. Reg is just a data type in the Verilog. What it maps to in logic is down to the behaviour in the code. It is just unfortunate they chose the name "reg"