Honored ContributorThe megafunctions LPM in Quartus... do they refer to existing blocks (hardware) on the fpga with ready written verilog codes to call them? or are they fully codes?
*More questions coming if it's ok
Honored ContributorSome megafunctions are implemented entirely in soft logic. Some like altpll (an Altera-specific megafunction, not an LPM megafunction) are just dedicated silicon. Some like altsyncram and lpm_mult can use RAM blocks and DSP blocks or logic resources. Some like altlvds_rx/altlvds_tx and alt2gxb can or must use dedicated silicon for SERDES or high-speed transceiver blocks but even then might include some logic resources.
Honored ContributorThanks Brad.
Another question: Say I'm doing a design of a digital block, say an adder, and I have tested the code with testbench in Modelsim at software level. Now when I have programmed the code to the fpga, how do I enter a set of inputs to test the fpga? What are the ways that I can enter inputs to the programmed block? Is there a memory somewhere on the board that can generate and store the input data?Honored ContributorSee the chapter on In-System Sources and Probes in Volume 3 of the Quartus handbook. The sources part is the only thing that comes to mind for stimulating logic in the FPGA without doing it through the signals on the board driving the input pins.
That volume of the handbook has some additional ways like SignalTap to observe signals similar to what you would do in simulation.Honored ContributorI am using the free Quartus. I just found the Quartus handbook from the net.
Will it apply? Or is the handbook mainly for subscribed Quartus? Thank you.Honored ContributorThe Quartus handbook applies the same to the Web Edition and Subscription Edition for those features that are available in the Web Edition.
Honored ContributorThis is a hello_world question. Can't be more newbie than that!
I did the "My First Nios II Software Design" tutorial using the IDE flow. It did what it's suppose to do, but I need to know who is saying hello to who? :o So if it the console in Nios II IDE states "Hello from Nios II" it means that communication with the Nios in the FPGA is fine i.e. the software is controlling the Nios II in the FPGA to send back to the PC console to say hello? Is that what it's doing? :o. Maybe I need some sleep.Honored ContributorAssuming that you've got your byteblaster (or USB blaster) connected to your NIOS board and you've downloaded the Hardware configuration and then downloaded your hello world software...
then yes, the message in your NIOS IDE console is coming from the board - your NIOS hardware and hello world software has worked. If you're not convinced then change the message in your software, compile it and download it again and you should get your new message.
