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Dan18
New Contributor
New ContributorNewbe Question: Quartus lite -- installing new ip (for audrino Vidor)
Hello,
I am using Quartus lite to work with the Audrino Vidor which includes a Cyclone 10 FPGA and am trying to get a sample project working [1].
After compiling i get an error that one of the I...
sstrell
Super Contributor
Super ContributorWhat is the exact error you are getting?
What is the file format of the IP? HDL code in .v or .vhdl? How are you instantiating the IP in your design?
