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set_output_delay -clock FTDI_CLK_ext -max 11.0 ]
set_output_delay -clock FTDI_CLK_ext -min 0.0 ]
Be correct to constrain AC[3] (which is the WR# signal) so that its setup time is at minimum 11ns and its hold 0ns... or am I completely missing the point.
Also if you set a constraint and timequest fails. You recompile your design so that it can be refit. If the clock and data delays are still too long to meet your timing requirements how do you proceed further after this?
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The timing constraints are OK, I assume that FTDI_CLK_ext is supplied by the FT245 chip.
If after recompiling the timing fails, you have to inspect the failing paths using the report-timing function in TimeQuest itself. Look through the datapath to find out where the bottleneck(s) are.
Now with 60MHz and 11 ns setup time you almost have to register anything going to the FT245 chip and very likely use IO-registers.
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