Honored Contributor
Honored ContributorCheers for the help an advice... unfortunately I have no byteblaster or other JTAG type device in order to use Signal Tap, as with the Morph board you program the FPGA over the USB interface... :(
I am only ever reading in 2400 bytes at a time then there are large gaps either side, as I read the first and final line of a frame, then stop reading anything into the fifo using a flag that signals the end of the first frame. The fifo is 4096 bytes long, so I shouldn't be losing data there, and the TX BUFFER in the FT2232 is defaulted to 4KB but I have it set to its maximum of 64KB, so I wont be trying to write to a full buffer there or anything either! Also, with respect to the FIFO Flags, my logic ensures that I stop reading from it when its empty, and can't write to it if its full.... its the fact that I am getting some double reads of data and stuff that is confusing the hell out of me... and as I have only just graduated and jumped into this with both feet; I am kinda feeling that I don't quite have the knowledge or the tools to crack this nut just yet! I have a feeling it is something that can't really be solved over the forum, there was just the hope, that someone may suggest something that would seem obvious to check to them, but that I may not have even considered due to my lack of experience with FPGA's Once again, cheers for your help and your TimeQuest guide... and I am sure you'll hear a eureka on the forums if i crack it! Regards, Lee H
