Honored Contributor
Honored ContributorWell TimeQuest may seem happy, but I am still getting timing errors somewhere...
My design simulates in ModelSim, I am not getting any errors from TimeQuest but I feel like I am still getting some timing errors in the actual implimentation on hardware as I am loosing some data bytes, and getting repeated reads of other data bytes within my log files, and I am struggling to work out where in my design they are coming from. I have a dual clocked FIFO, to which I am trying to write 1 line of 800 24-bit pixels (2400 bytes) using my LVDS_CLK, and the data should be clocked out of the FIFO using the FTDI_CLK. As I am using the Morph-IC-II Board the FT_CLK is provided by the FT2232H USB Bridge chip. When the data is clocked out of the FIFO in the FPGA it should be clocked into the TX FIFO on the FT2232H, which will await a command which it recieved over USB before transmitting it to the application. I am struggling to find where my data is getting mangled but think its probably due to timings somewhere within the FPGA... but am struggling to get any further as I dont have any Unconstrained paths, or things failing setup or hold...so being new to this I am kind of at a loss.... Any help on this is greatly appreciated. Regards, Lee H
