New to TimeQuest... Need help to add constraints and delays!

Is this an I/O port? Looking at the Data Path tab, I'd guess it's internal to the FPGA.

Your transfer is from rising edge to falling edge(i.e. the latching logic triggers on the falling edge), so it defaults to a half-cycle setup relationship, or 3.75ns. Your latch clock is on a PLL, which basically removes the clock tree delay, but your source clock is not. So the clock skew completely cuts into your setup requirement. Your data path delay is less than 2ns, but because of these two things it's still not enough.

Is the 3.75ns requirement your intended transfer? If so, can the data path be shorter? I doubt it can be 800ps shorter, but might be. Can you change the clocks to make the requirement/skew more palatable? Reading the document will help with understanding, but won't provide a solution, since this is unique to your design.