--- Quote Start ---
So is it possible to do complete development of hardware in the FPGA without writing any HDL? Can IP cores such as a PCIe core be developed from OpenCL?
I have downloaded a "hello world" OpenCL generated rbf image from the Bittware website. It seems that this already has some PCIe core as it is detected over PCIe when I start the host. Would this image of been generated completely using OpenCL or with a combination of Altera's IP cores for use in Qsys etc. ?
Thanks for the info.
--- Quote End ---
You can look at the designs examples on the Altera's OpenCL page. The programmer only develops the OpenCL program (.cl) that does the computation and the host program that launches this OpenCL program. All the communication between the host and the FPGA is automatically handled by the tool. You do not need to write a single line of Verilog/etc.
Honored Contributor
