Negative Slack after constraing the clocks

Rysc,

I compiled my design an ran TimeQuest again with the same SDC file. There are still violations:

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Setup violation on:

pll|clk[2]: -4.961 slack, -777.139 End Point TNS

Hold violation on:

pll|clk[2]: -4.464 slack, -12.867 TNS,

48MHz....safe_q[0]: -0.610 slack, -0.610 TNS,

96MHz....safe_q[0]: -0.007 slack, -0.007 TNS

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How do i solve these? Should i put constraint on the paths? There are a lot of Failing Paths for the pll.

EDIT: I solved the Hold violations by putting a Multicycle constraint of 1 cycle between the clocks. The Setup violation is between Nodes, and a lot of nodes, instead of clocks, should i use the same multicycle approach?