Negative Slack after constraing the clocks

[QUOTE=Rysc;178810

- Why not use derive_pll_clocks instead of manually entering the generated clock assignments?

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Hi Rysc,

This is somewhat OT here, but I take advantage of your comment to ask your expert advice on this subject.

I often chose the create_clock command instead of derive_pll_clocks in order to define the clock domains with simple mnemonic names: i.e. clk50mhz whereas derive_pll_clocks would have generated obscure names like inst5|altpll_component|auto_generated|pll1|clk[0]

I've never used TQ extensively, since i focused mainly on other fpga design issues, so I never inquired if there was a better way to do this, still exploiting the automation offered by derive_pll_clocks. I think it's possible. But how?