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You can't trust the results post-synthesis, especially with zero IC delay. Hold violations are because a signal is too fast, and if you zero out the IC delays, your making it faster than it will ever really be. I find post-synthesis TimeQuest useful for setting up my .sdc, making sure there are no syntax errors, making sure it's analyzing the things I want correctly, i.e. how paths will be analyzed, not whether or not they meet timing. Then I run a full compile to look at the fit results.
I see you're doing create_clock on the outputs of counters. create_clock will act as if the clock starts exactly at that point. This is fine for analyzing the domain by itself, but if you want to know its relation to other domains, i.e. if you have a path going from ...safe_q[1] to ...safe_q[0], you won't get the correct analysis because the clock path before these registers are completely ignored. If you want the clock tree up to that point analyzed, use create_generated_clock.
- Why not use derive_pll_clocks instead of manually entering the generated clock assignments?
- There is no set_clock_groups, so all your clocks are related and any paths between them will be analyzed. This might be what you want, but you may get errors on paths crossing domains that you don't care about.
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Thanks for the reply, Rysc.
I haven't constrained any paths yet and i made the clock constrains using the Reports Clocks report window, then i right clicked them and went to "Edit Clock Constrains", it generated the pll that way. Is it better to use derive_pll_clocks?
All my clocks are generated from the PLL clock of 96MHz, so they are related. The only clock that is not related is the spi_clock, which comes from a SoC master. Should i declare it differently?
I'll run the full compilation to see if the hold delays goes away. Thanks for helping me, i'm still learning about FPGAs and how to use TimeQuest.
EDIT: i only ran the time analysis after the post syntesis because the TimeQuest Training states that this is the normal design flow.
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