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Altera_Forum's avatar
Altera_Forum
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9 years ago

Need to write timing constraints for PLL generated clocks?

Dear all, I managed to write an SDC file for the external clock with: create_clock -period 40.00 -name {CLK_25MHz} [get_ports {CLK_25MHz}] This clock is the input of a PLL that genera...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Well, it seems I mainly have syntactic issues. With your help I could make it work with a unique name for each clock, but then it worked also with a vector of clocks. One point is that after the '\' at the end of the line, no space character is allowed. It is useful to "Read SDC File" in TimeQuest, but only possible when the design Fit is complete...

Thanks a lot