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Honored Contributor
Honored ContributorNeed to write timing constraints for PLL generated clocks?
Dear all, I managed to write an SDC file for the external clock with: create_clock -period 40.00 -name {CLK_25MHz} [get_ports {CLK_25MHz}] This clock is the input of a PLL that genera...
Altera_ForumHonored Contributor
Honored ContributorI'm willing to bet that vectorizing the clocks is the issue ([0],[1], etc.). Each clock should have a unique name and not be vectorized.
