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Altera_Forum's avatar
Altera_Forum
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15 years ago

Need some helping testing some VHDL Code

I have a project comming up, and I have some VHDL code that I really want to test. Basically what I have so far... Is that I created a symbol file from quartus, and this gets created with no ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

this would be in a seperate testbench file. You can create an input vector for stimulus if you want - but you would have to somehow read it into the unit under test, which is usually done in a testbench.