Honored Contributor
Honored ContributorHi Miao,
Thanks for your responses, they show that you had already considered my concerns, and appreciate the difficulty of your task :) --- Quote Start --- A quetion came to me when I read this. Is the serial interface of the FPGA still usable after configuration? If not, it seems that I can only use a double shift-register behind the inputs if I want to use serial flash and I can not make this out with my DE2 board. --- Quote End --- It depends on the device you are planning on using, and the configuration mode you select. I'm fairly certain you can configure the interface as an SPI flash master, since that is how you would read the flash from a NIOS II processor. However, I'm not sure you can change the direction of DCLK and make it an input, eg., so that you have an SPI slave. I would not be too concerned about that though. Your application can easily use the SLD Virtual JTAG component and use JTAG directly to access the FPGA fabric. The SLD Virtual JTAG gives you a way to bring the JTAG signals and some parallel signals into the FPGA fabric - but not the scan chain of the FPGA fabric. Here is some notes; https://www.ovro.caltech.edu/~dwh/correlator/pdf/vjtag.pdf the JTAG-to-Avalon-MM bridge is based on a variation of this component https://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_jtag_to_avalon_analysis.pdf Good luck with your testing! Cheers, Dave
