Need some help of SRunner Tools! Need some related files!

Hi Miao,

Thanks for the additional details. However, I still think your idea will suffer from a lack of information from the manufacturer.

I have FPGAs that have functional errors, i.e., a bad logic cell inside them somewhere. I tried finding an Altera tool that would let me scan and test the entire chip, but that information is proprietary, and I could not locate any tools. The BIST BSDL files only provide information on the external I/O pins, not the internal scan chains, so they are no help when trying to test an FPGA internals.

The only way I could see scanning and detecting errors in an FPGA is to run scan vectors through the internal scan chains that are used when the device is configured, i.e., a test system would exercise the LUT/ALM logic by using the scan chain to load the LUT/ALM lookup table, and then use the scan chain to scan in new input values and read the output values, and confirm they match the expected values. All of these tests would be performed on a device that is not configured. You cannot use the EPCS interface for this, since it just reads a single data stream and configures the device configuration SRAM cells, i.e., you cannot read any scan chain details via the EPCS interface.

You are proposing configuring a device and then using the user-programmable part of the FPGA for testing itself. This approach has a serious problem, eg. lets say you have an FPGA with a bad LUT/ALM. How do you identify that? Perhaps you are lucky and the LUT/ALM is used to implement a register and a bit in that register cannot be changed. But what happens if the bad LUT/ALM is in the address decoding logic, and you can never reach a particular register or block of registers?

How about this question; if I ask you to scan test the top-row of LUTs/ALMs in an FPGA, how will you do that? Using only the user fabric and the standard Altera tools, you would have to create an HDL instance that exactly matches an LUT/ALM, then you would have to force the place-and-route tool to place those components along the top row (which you might be able to do with the floorplanning tools), and then you would have to link all that logic together in a scan chain so you could test it ... that scan chain would require logic, and most likely need to use the logic you are trying to test. I cannot see how it would be possible to provide 100% test coverage using the fabric to test itself.

I would really like to have a tool that would allow me to perform a complete verification of the functionality of the internals of an FPGA. However, given that Altera does not already provide one, I'm not sure you will succeed.

Cheers,

Dave