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Altera_Forum's avatar
Altera_Forum
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9 years ago

Need help with understanding this VHDL assignment

Taking a course in VHDL and it seems very fun so far.

However, I am stuck on trying to understand this assignment, it is about creating a 4-bit carry look ahead adder in VHDL but the adder should not have a generate or a propagate output. What does that mean? How am I supposed to create a carry look ahead without a generate or a propagate? I am interpreting this as I am supposed to replace generate with (A AND B) and propagate with (A XOR B). What do you guys think?

Thanks in advance :)

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    According to the way I interpreted your question, it should simply mean that generate/propagate signals don't belong to the entity of your adder. The concept is basically the fact that generate/propagate signals are internally used by the adder to evaluate carries, but your entity should only have sum and c_out as outputs.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    9 years ago

    Please reword your question and post the source of what is your trouble.

    A,B are scalars or vector? Are you building a full adder cell?