Need help with this vhdl code

I have this code and the problem is that it says that G does not agree with his usage as a boolean operator when I try to give value to Z1 and I cant see the error. Please help and thank you.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity COM_SM_4 is
port(A, B: in std_logic_vector (3 downto 0);
Z: out std_logic_vector (3 downto 0));
end COM_SM_4;
architecture BH of COM_SM_4 is
component deco_sm_9
port(I: in std_logic_vector (3 downto 0);
VABS: out std_logic_vector (3 downto 0);
SIG: out std_logic);
end component;
signal VA, VB, Z3, Z2 ,Z1: std_logic_vector (3 downto 0);
signal SA, SB, G, E: std_logic;
begin
V1: deco_sm_9 port map (A, VA, SA);
V2: deco_sm_9 port map (B, VB, SB);
G <= '1' when unsigned(VA) > unsigned (VB) else '0';
E <= '1' when unsigned(VA) = unsigned (VB) else '0';
Z1 <= VB when G or B = '0' else VA;
Z2 <= A when G or B = '0' else B;
Z3 <= Z1 when SA = '0' and SB = '0' else
VA when SA = '0' and SB = '1' else
VB when SA = '1' and SB = '0' else
Z2;

Z <= "0000" when Z3= "1000" else Z3;

end BH;