Need help with RGMII RX violated hold slack

Hi folks,

I need a little help with some timing issue. In a few words, I have a RGMII interface which I want to communicate with the Marvell PHY on the Cyclone V GT development board.

In my .sdc file, I have followed the AN477 example on connecting an fpga to an external phy device when the delay option is enabled (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/an/an477.pdf), yet I get a large hold slack violation:

http://www.alteraforum.com/forum/attachment.php?attachmentid=13030&stc=1

I think my problem comes from the fact that the clock delay is quite high. How can I reduce it so that the "Data Required" ends before the next data arrival?

Regards,

Smith