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Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- http://img338.imageshack.us/img338/9634/123mas.jpg i need to connect data_out[7..0] to the second block to M[1..0], but i need that only bits, data_out(0) and data_out(1) will be connect to this vector M. and for example data_out(3) to the FIN_RE node and data_out(4) to FIN_UN... how can i do this???? thank you Alex. --- Quote End --- Hi, Please check the attachment, you can see the 4 bits of AccDelay[3..0] are assigned to a[1],a[3],a[5],a[7] respectly!