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Altera_Forum's avatar
Altera_Forum
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11 years ago

Need help in verilog file creation

I have a file which is extended to .tdf (Text Design File) from altera library. I want to convert it to traditional verilog code. Can anyone help in this regard? thanks, mahee
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

If you download Xilinx ISE tools, it has a program called XPORT that allows you to convert AHDL files (.tdf) to VHDL or Verilog. Otherwsie you'll have to do it manuallly