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Altera_Forum
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11 years ago

Need advice about coding style

Hello I'm Alex and I am novice for VHDL coding. if my english awful pls forgive me. I trying to understand VHDL PROCESS statement. I try with 1bit full adder with carry save function in Quartus2 v...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Tricky , you shed the light for me. seriously.

the both state machines are Melay machine. I know a lot of about state machines from theory.

it is better to follow style with two separate processes for describing fsm. so model and synthesis will be similar.

be aware : you can get unexpected clock-enable pins instead of asynchronus reset with styles as above.