Need advice about coding style

How about such cutting for sensitivity list when describing FSM? I know that is very badexample with impure function instead of process but ... quartus eats it up.

library ieee;
use ieee.std_logic_1164.all;
entity fsm is
    port(
        clk,
        enable_SM,
        start,
        pk_eq_k,
        pn_eq_n : IN std_logic;
        pk0,
        pkp1,
            pn0,
        pnp1 : OUT std_logic
    );
end fsm;
architecture v1 of fsm is
    type state_type is (s1, s2, s3, s4);
    impure function next_state(st : state_type) return state_type is
    begin
            case st is
            when s1 =>
                if start= '1' then
                    return s2;
                else
                    return s1;
                end if;
            when s2 =>
                return s3;
            
            when s3 =>
                if pk_eq_k = '0' then
                    return s3;
                else
                    return s4;
                end if;
            
            when s4 =>
                if pn_eq_n = '0' then
                    return s4;
                else
                    return s2;
                end if;
            
            end case;
    end next_state;
signal
    st : state_type;
begin
    process(enable_SM, clk)
    begin
        if enable_SM = '0' then
            st <= s1;
        elsif rising_edge(clk) then
            st <= next_state(st);
        end if;
    end process;
    
    pk0 <= '1' when (st = s1 or (st = s4 and pk_eq_k = '1')) else '0';
    pkp1 <= '1' when st = s3 else '0';
    pn0 <= '1' when st = s2 else '0';
    pnp1 <= '1' when st = s4 else '0';
    
end v1;

The code above ... struck me so / really assignment to signal operators imply implicit processes . so i change a little bit behaviour to fsm

architecture v2 of fsm is
    type state_type is (s1, s2, s3, s4);
    signal st : state_type;
    
    procedure state_transition is
    begin
            case st is
            when s1 =>
                if start= '1' then
                    pk0 <= '1';
                    st <= s2;
                else
                    pk0 <= '0';
                    st <= s1;
                end if;
                pkp1 <= '0';
                pn0 <= '0';
                pnp1 <= '0';
                
            when s2 =>
                pn0 <= '1';
                pkp1 <= '1';
                pk0 <= '0';
                pnp1 <= '0';
                st <= s3;
            
            when s3 =>
                if pk_eq_k = '0' then
                    pk0 <= '0';
                    pkp1 <= '1';
                    pnp1 <= '0';
                    st <= s3;
                else
                    pk0 <= '1';
                    pkp1 <= '0';
                    pnp1 <= '1';
                    st <= s4;
                end if;
                pn0 <= '0';
                
            when s4 =>
                if pn_eq_n = '0' then
                    pnp1 <= '1';
                    st <= s4;
                else
                    pnp1 <= '0';
                    st <= s2;
                end if;
                pkp1 <= '0';
                pn0 <= '0';
                pk0 <= '0';
            
            end case;
    end state_transition;
begin
    process(enable_SM_n, clk)
    begin
        if enable_SM_n = '1' then
            st <= s1;
            pn0 <= '0';
            pkp1 <= '0';
            pk0 <= '0';
            pnp1 <= '0';            
        elsif rising_edge(clk) then
            state_transition;
        end if;
    end process;
end v2;

but all is fine until you you catch multiple assignments.

by the way ... (why my rang became as written? is it joke?)