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The sensitivity list for a clocked process should only contain the clock and the reset signals. If you add the wrn and wrk signals to the list, you will create a design that will behave differently in a simulator and on a real FPGA. Quartus will ignore your sensitivity list and just synthesize as if it was (r, clk) so if you want to simulate it correctly in Modelsim you should write it as is in your code.
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I have tried to remove one and with standard option set the quartus reports me that i should include them in process-sensitivity list xD
and if you want trully asyncronus modeling -> let's enter the process, stop it through breakpoint in statements for clock transition, then manually change signal 'r' value to one that send command reset to your schematic. and wait when the reset occur . will we have glitch?
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